The present invention relates generally to semiconductor processing and, more particularly to methods for etching organic insulating layers.
The present day semiconductor industry continually strives to increase device performance by reducing device dimensions and increasing device packing densities. For a given chip size, increasing the device packing density can be achieved by reducing the vertical and lateral distance separating active devices, with a resulting reduction in dielectric thickness (often referred to as inter-metal oxide or IMO) between layers. Unfortunately, reducing dielectric thickness increases interlayer capacitance, which results in diminished high frequency performance of the integrated circuit.
In integrated circuits, conventional insulating layers, such as silicon dioxide and silicon nitride, generally have dielectric constants xe2x80x9ckxe2x80x9d of about 3.9 and above. For example, the dielectric constant of silicon dioxide is about 3.9 and the dielectric constant of silicon nitride is about 9.0. As the feature scales shrink in IC devices it becomes desirable to reduce the dielectric constant of the insulating layer to reduce the inter-layer capacitance.
Since the dielectric constant xe2x80x9ckxe2x80x9d of some organic materials, such as FLARE from AlliedSignal, Inc. and SiLK from Dow Chemical, is generally less than 2.7, organic materials can be used as a low-k organic insulating layers for chip fabrication. However, the organic materials present problems during a conventional etch process. Most notably, etching organic materials using conventional methods results in the organic insulating layer having via sidewalls that are undercut and bowed.
FIG. 1A is an illustration showing a cross-sectional view of a prior art integrated circuit structure 10 having an organic insulating layer 12 prior to a plasma etch. More particularly, integrated circuit structure 10 includes an organic insulating layer 12, a silicon dioxide hardmask layer 14 disposed above the organic insulating layer 12, and an organic resist mask 16 formed above the silicon dioxide hardmask layer 14. FIG. 1B shows the integrated circuit structure 10 after etching the silicon dioxide hardmask layer 14 by a suitable oxide-etch process though the resist mask 16. FIG. 1C shows the integrated circuit structure 10 after etching (xe2x80x9coxidizingxe2x80x9d) the organic insulating layer 12 using conventional oxygen containing gases. A conventional etch of organic low-k materials in a plasma chamber typically employs oxygen containing gases such as O2, CO2, and SO2. In the presence of plasma, oxygen atoms and ions are formed. Atomic oxygen reacts with organic material and forms CO, H2, and CO2 as by products. However, spontaneous reactions between the atomic oxygen and the organic low-k materials occur. The reactions between the atomic oxygen and the organic low-k insulating layer cause isotropic etching, which results in undercut and bowing of the organic insulating layer 12 as illustrated by the bowed profile of sidewalls 18.
To counter undercut and bowing in the sidewalls 18, gases such as C2H4 are sometimes used during organic etch. FIG. 1D shows the integrated circuit structure after etching the organic insulating layer 12 using C2H4 containing gases. The C2H4 forms a CxHy polymer on the etch sidewall during the etch process. The result is a sidewall 18 which is sometimes less undercut and bowed than the sidewall profile resulting from conventional oxygen containing gases. However, this approach is difficult to control, and does not always result in an improved sidewall 18 profile. The amount of improvement depends on the parameters used to control the sidewall 18 profile, resulting in an approach which is delicate and lacking robustness.
Another approach used to counter undercut and bowing in the sidewall 18 profile during an organic etch is the use of high energy sputtering. Prior art FIG. 1E shows the integrated circuit structure 10 after etching the organic insulating layer 12 using high energy sputtering. The high energy sputtering causes sputtering of SiO2 from the silicon dioxide hardmask layer 14 to create sidewall passivation. However, the high energy sputtering can cause damage 20 to the hardmask layer 14 during the etch process. In addition, when a deep etch is needed, high energy sputtering is often insufficient to cause sidewall passivation coating near the bottom of the via, again resulting in an undercut and bowed sidewall 18 profile.
All of the organic etch approaches discussed above fail to provide a consistent, robust etch process which provides a sidewall profile in an organic insulating layer that is not undercut or bowed. Accordingly, there exist a need for a robust organic etch process that does not cause damage to the IC, and provides better sidewall profiles.
The present invention meets the aforementioned requirements by providing a process that etches organic insulating layers utilizing an oxidizing gas and a passivation gas. The passivation gas reacts with oxygen atoms or oxygen molecules to form a nonvolatile passivation film which deposits on the sidewalls of vias being formed in the organic insulating layer. The passivation film provides sidewall passivation which essentially inhibits isotropic etch of the organic insulating layer. Thus, the resultant via sidewall profile in the organic insulating layer is essentially vertical with respect to the plane of the insulating layer.
One aspect of the present invention teaches a method for anisotropically etching an organic insulating layer through an aperture in a mask layer. A substrate, with an organic insulating layer and an overlying mask layer having an aperture, is introduced into a processing chamber. A plasma is then developed within the chamber from an oxidizing gas and a passivation gas. The passivation gas is preferably either a silicon containing gas or a boron containing gas, or both. The ratio of the oxidizing gas to the passivation gas is preferably at least 10:1. An inert carrier gas may also be provided. The plasma is then used to etch the organic insulating layer through the mask layer.
Another aspect of the present invention teaches an etch system for organic layers. The organic etch system includes a chamber which is receptive to a substrate provided with an organic insulating layer to be etched. Also included is a gas inlet mechanism connecting an oxidizing gas and a passivation gas source. The passivation gas is derived from the group including silicon containing gases and boron containing gases. The ratio of the oxidizing gas to the passivation gas is preferably at least 10:1. Further included in the system is a pair of electrodes disposed within the chamber, and an RF generator coupled to the electrode pair so that a plasma is formed with the oxidizing gas and the passivation gas which etches exposed portions of the organic insulating layer.
As stated above, the present invention has the ability to produce accurate vias having essentially vertical sidewall profiles in organic insulating layers. The ability to produce accurate vias allows the use of organic low-k insulating layers in integrated circuit fabrication. The organic low-k insulating layers lower the interlayer capacitance, and thereby increase high frequency performance of the integrated circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following descriptions and a study of the various figures of the drawings.